1. Field of the Invention
This invention relates to memory cells, and particularly to electrically erasable and programmable read only memories (EEPROMs) used as nonvolatile semiconductor storage systems to store both digital and analog signals.
2. Description of Related Art
As is well known in the art, an EEPROM cell utilizes a floating polysilicon layer, conventionally called a floating gate, positioned between but insulated from a channel region and a control gate. The channel region is formed between a source and a drain region. The floating gate retains charges, thereby varying the threshold voltage of the transistor. The threshold voltage is the minimum voltage applied to the control gate to turn on the transistor, i.e. to allow current to flow between source and drain regions. Each EEPROM cell conventionally stores only one bit of data, i.e. either a "0" or a "1". For example, a stored "0" in one convention is associated with an "on" state while a stored "1" is associated with an "off" state.
To read the data stored in a memory cell, a voltage is applied across the source and drain regions while another voltage is placed on the control gate. The amount of current flowing between source and drain regions as a result of these applied voltages determines whether the transistor is "on" or "off". In the "on" state, the channel is conducting and current flows between the source and drain regions, whereas in the "off" state, the channel is not conducting and no current flows between the source and drain regions. A memory cell can be programmed to the "on" or "off" state by changing the amount of charge retained on the floating gate so that the threshold voltage is either higher than the applied control gate voltage (resulting in an "off" state) or lower than the applied control gate voltage (resulting in an "on" state).
Writing data into a memory cell typically includes two steps. First, the cell is erased by removing charges from the floating gate, and then the cell is programmed by charging the floating gate according to the data to be stored. Transferring charges to and from the floating gate is achieved either by hot electron injection or tunnelling. During hot electron injection, electrons, accelerated in a high electrical field across the channel region, acquire the energy necessary to overcome the energy barrier imposed by the insulation formed between the channel region and the floating gate. During tunneling, electrons drift across the energy barrier of the insulation formed between the floating gate and other nearby electrodes, e.g. the source region, the drain region, or the channel region, by applying a high electrical field across the insulation. A conventional EEPROM cell usually relies on tunneling for both programming and erasing operations. To ensure cell-by-cell erasability and to avoid read errors caused by over-erase of some of the unselected cells, a separate select transistor is typically used to disconnect the drain regions of the unselected cells from the selected cell during erase and read operations. However, this additional transistor increases the size of the memory cell array.
A common trend in the semiconductor memory industry is to reduce the size of the memory array to achieve higher cell density on a single chip, thereby lowering the cost per bit. One method of reducing the array size is to eliminate the select transistors, as disclosed by Masuoka, et al. in an article entitled, "A new flash EPROM cell using triple polysilicon technology", IEDM Proceedings, page 464, 1984. Masuoka et al. reduced array size by using a split channel structure shown in FIGS. 1A and 1B and a flash erase scheme. A split channel structure is conventionally defined as two transistors, a floating gate storage transistor and a select transistor, sharing a channel region. The term "flash" refers to the fact that an entire array or a relatively large block of memory cells is erased simultaneously.
FIGS. 1A and 1B show cross-sectional views of the memory cell 100 of Masuoka et al. along a bit line and a word line, respectively. Referring to these figures, the memory cell 100 erases using electron tunneling from floating gate 101 to a separate erase gate 102. Erase gate 102 eliminates the problem of having a very high voltage on source region 105 or drain region 106. However, the amount of overlap between erase gate 102 and floating gate 101 is critical, thereby increasing manufacturing complexity and lowering yield.
Advances in methods of growing oxide have allowed thinner layers of oxide to be used as insulation, thereby reducing the required threshold voltage for tunneling. FIG. 2 illustrates a stacked gate EEPROM cell 200 disclosed by Mukherjee et al. in an article entitled "A Single Transistor EEPROM Cell And Its Implementation In A 512K CMOS EEPROM", IEDM Proceedings, page 616, 1985. Mukherjee et al. eliminated the need for erase gate 102 (FIG. 1B) by allowing electrons to tunnel from floating gate 201 to source region 205. The thin insulation layer 204 facilitates this tunnelling. However, because electrical erasing is not self-limiting, floating gate 201 is likely to be over-erased and become positively charged after erasing. This positive charge on floating gate 201 turns memory cell 200 into a depletion mode transistor. If the floating gate transistor becomes a depletion-mode transistor after being over-erased, the transistor turns on even if it is unselected, thereby causing read errors of the selected cell.
To overcome this over-erase problem, G. Samachisa, et al. disclosed a split channel structure in an article entitled, "A 128K Flash EEPROM using Double-Polysilicon Technology", IEEE Journal of Solid State Circuits, Vol SC-22, No. 5, page 676, October 1987. Referring to FIG. 3, Samachisa et al. added a series select transistor 307 to stacked gate EEPROM cell 200 to control the channel conductance. In this manner, if series select transistor 307 is off, no current flows between the source region 305 and the drain region 306, even if the floating gate transistor 300 is in a depletion mode. Like cell 200, cell 300 of Samachisa has a thin gate insulation 304 to allow electron tunneling from floating gate 301 to drain region 306.
Another method to overcome the over-erase problem was disclosed by V. N. Kynett, et al. in an article entitled, "An In-System Reprogrammable 32K.times.8 CMOS Flash Memory", IEEE Journal of Solid State Circuits, Vol. 23, No. 5, page 1157, October 1988. Kynett added program and erase verify circuitry (not shown) to the stacked gate flash-EEPROM cell 200. However, Kynett, like Mukherjee et al. and Samachisa et al. relies on the thinness of the gate insulation for electron tunneling, thereby creating problems in reliability and manufacturing yield.
Therefore, other methods to reduce array size, such as storing more than one bit of data per memory cell, have been devised. The concept of storing multiple bits of data per memory cell is essentially the same as storing an analog signal in a memory cell. Due to the advancement in digital signal processing, an analog signal is often converted into and represented by a string of binary code or a word of multiple bits. The higher the number of bits representing a sampled and held analog signal, the higher the accuracy of the signal represented. Thus, an EEPROM cell that stores multiple bits of data can effectively store a complete sampled and held analog signal. The accuracy of reproducing a stored analog signal typically depends on the full range of cell current and the signal to noise ratio.
An EEPROM cell, disclosed by Bleiker et al. in an article entitled "A Four-State EEPROM Using Floating-Gate Memory Cells", IEEE Journal Of Solid State Circuits, Vol. SC-22, No. 3, pages 460-463, June 1987, stored two bits of data. The four distinguishable states of this cell were defined by the levels of cell current detected. Each state was characterized by an upper and lower current limit. However, as is well known to those skilled in the art, to accurately detect the data stored in the memory cell within a reasonable read time, the current level used to characterize the least significant bit (LSB) must be large enough to yield an acceptable signal to noise ratio. Moreover, for a given LSB, the range of cell current must be increased to store additional bits of data per memory cell.
To increase cell current without changing the channel length, prior art methods typically increased the transistor width. However, an increase in transistor width increases memory cell size for conventional planar cells (such as cells 100, 200, and 300), i.e. cells which have source, drain and gate regions above and/or near the surface of the substrate.
To decrease memory cell size while providing increased cell current, Yoshida, et al. disclosed a vertical EPROM/EEPROM cell in U.S. Pat. No. 5,049,956, issued Sep. 17, 1991. Referring to FIG. 4 of this specification, vertical stacked gate EEPROM cell 400 is formed on the side wall 406 of a trench 407 etched to source region 402 which is buried in substrate 401. The width of cell 400, which equals the perimeter of trench 407, is roughly four times that of planar cell 200 (FIG. 2) but occupies the same silicon area. However, this structure, like cell 200, lacks a select transistor and thus has no cell-by-cell erasability. Moreover, the thin gate insulation 408 which overlies the entire channel region 403 induces reliability and yield problems. Further, the uneven topography of cell 400, created by the projection of floating gate 405 above the surface of the array, further worsens reliability and yield.
Therefore, a need arises for a reliable memory cell capable of storing multiple data bits while occupying a small surface area of the chip.